RESYNC=0, FSTWR=0, WRLATR=0
DDR Control Register 29
| WRLATR | Write Latency Reduction enable 0 (0): Disable 1 (1): Enable |
| RESERVED | Reserved |
| FSTWR | Fast Write 0 (0): The memory controller issues a write command to the DRAM devices when it has received enough data for one DRAM burst. Write data can be sent in any cycle relative to the write command. This mode also allows for multi-word write command data to arrive in non-sequential cycles. 1 (1): The memory controller issues a write command to the DRAM devices after the first word of the write data is received by the memory controller. The first word can be sent at any time relative to the write command. In this mode, multi-word write command data must be available to the memory controller in sequential cycles. |
| RESERVED | Reserved |
| QFULL | Queue Fullness |
| RESERVED | Reserved |
| RESYNC | Resyncronize 0 (0): No effect 1 (1): Initiate |
| RESERVED | Reserved |